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类型SEMI M15-0298 POLISHED WAFER DEFECT LIMITS TABLE FOR SEMI.pdf

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    SEMI M15-0298 POLISHED WAFER DEFECT LIMITS TABLE FOR M15 0298
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    SEMI M15-0298
    POLISHED WAFER DEFECT LIMITS TABLE FOR SEMI-INSULATING
    GALLUM ARSENIDE WAFERS
    NOTE: This entire document was revised in 1998
    1 Purpose
    1.1 This document defines the maximum number of defects, by type, that an acceptable polished Semi-insulating
    Gallium Arsenide(GAAS)wafer may exhibit
    2 Scope
    2. I This document, established separately from SEMI M15, in accordance with the latest requirements for the
    material in advanced applications, covers polished semi-insulating GAAS wafers. The defect limits table can also
    be applied to conducting Gaas wafers, except for the specification of Light Point Defects(LPD )mentioned here-
    Inafter. Polished shall refer to those wafers which have a specular chemical or chemical/mechanical fnish
    epplied to one side of the wafer, with the backside being as cut and etched, lapped and etched, ground and etched
    or polished. The definition of defects is covered in ASTM Practices F 523 and F 154
    3 Referenced Documents
    3 1 ASTM Standards
    F154 -Practices and Nomenclature for Identification of Structures and Contaminants Seen on Specular Silicon
    uraci
    1: 523 -Practice for Unaided Visual Inspection of Polished Silicon Slices
    Table 1
    Polished Wafer Defect Limits
    Maximum Defecls Maximum Defechs
    Limits
    Item t
    Characteristics- Pront Surface
    Prime Wafer
    est Wa
    arer
    Scratche
    Macroscratches
    None
    Maximum Numbcr
    3
    Maximum Lcngth
    Radius/2
    Microscralches
    Not Specified
    #,2
    Plls
    #⊥.2
    2 Diameter Slices
    5
    3 Diameter Slices
    15
    4"Diamclcr Sliccs
    Nonc
    30
    Haze
    Nonc
    Nonc
    #1,2
    Cavity/Voids
    None
    Non
    Contamination
    None
    #1,2
    I merican Society for Iesting and Materials, 100 Bar Labor Drive, West Conshohoken, PA 19428-2959
    SEMIM15-02980SEMI1989,1998
    Table 1, Polished Wafer Defect Limits
    Maximum Defecis
    Tem
    Characteristics- Front Surface
    Prime Wafe
    Test Wafer
    Notes
    Light Point Defects≥φ2.0wum
    2diamctcr Sliccs
    #2.3
    3 Diamclcr Sliccs
    #2.3
    4 Diameter Slices
    40
    #2.3
    Light Point Defects z/ 3.0 um
    Diamclcr Sli
    50
    #2.3
    3 Diamclcr Sliccs
    100
    200
    #2.3
    4 Diameter Slices
    200
    400
    2.3
    [Chp
    ps(≥0.5mm×0.3mm)
    None
    None
    8
    Tacks
    onc
    Dimples
    #1.2
    10
    Gallium Inclusions/Precipitates
    None
    #1.2
    Orange Peel
    None
    None
    #1.2
    Saw Marks
    one
    ations
    #1.2
    14
    wins
    nc
    #⊥.2
    M
    Defect Mc
    Defect
    Limits
    Item
    Characterislics- Back Surface
    Prime Wafe
    Test Wafe
    15
    taln
    2,4
    16
    Saw Marks
    Nonc
    #1.5
    17
    Chips(≥0.5mm×0.3mm)
    onc
    onc
    18
    19
    isted Defects #10. 14
    None
    1.2
    20
    Listcd Dcfccls #I. 2. 6
    NOTES
    These dc ccl limits arc mcan to apply only to thosc charactcristics which can bc sccn with the unaided cyc undcr high-intcnsity
    Imination according to ASTM Practicc F 523. Limits for othcr defects listed and dcfincd in this scction which rcquirc the aid of
    a microscope, preferential etching, or other apparatus must be agreed upon between supplier and user
    2. Peripheral Edge Allowance-the out
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