ECSS-E-ST-50-14C(31July2008).pdf

ECSS-E-ST-50-14C 31 July 2008 Space engineering Spacecraft discrete interfaces ECSS Secretariat ESA-ESTEC Requirements whetherornotinjurywassustainedbypersonsor propertyorotherwise;andwhetherornotlosswassustainedfrom,oraroseoutof,theresultsof,the item,oranyservicesthatmaybeprovidedbyECSS. Publishedby:ESARequirementsandStandardsDivision ESTEC, P.O. Box 299, 2200 AG Noordwijk The Netherlands Copyright: 2008 by the European Space Agency for the members of ECSS ECSSEST5014C 31July2008 3 Change log ECSSE5014A 19December2007 Firstissue ECSSE5014BNeverissued ECSSEST5014C 31July2008 Secondissue Editorialchanges. ECSSEST5014C 31July2008 4 Table of contents Change log.3 1 Scope.8 2 Normative references.9 3 Terms, definitions and abbreviated terms.10 3.1 Terms from other standards.10 3.2 Terms specific to the present standard .10 3.3 Abbreviated terms .11 3.4 Conventions .12 3.4.1 Bit numbering convention.12 3.4.2 Timing diagram conventions.12 3.4.3 Signal and signal event naming convention.13 3.4.4 Signal timing and measurement references.14 4 General.15 4.1 Introduction.15 4.2 Architectural concepts.15 4.2.1 Overview.15 4.2.2 General failure tolerance.16 4.2.3 Interface control during power cycling.17 4.2.4 Cross-strapping.18 4.2.5 Harness cross-strapping.19 4.2.6 Cable capacitance.22 5 Analogue signal interfaces.23 5.1 Overview .23 5.2 Analogue signal monitor (ASM) interface.23 5.2.1 General.23 5.2.2 Analogue signal monitor interface.25 5.3 Temperature sensors monitor (TSM) interface.27 5.3.1 Overview.27 ECSSEST5014C 31July2008 5 5.3.2 TSM acquisition layout .28 5.3.3 TSM acquisition resolution .28 5.3.4 TSM wire configuration.28 5.3.5 TSM electrical characteristics.29 6 Bi-level discrete input interfaces .37 6.1 Bi-level discrete monitor (BDM) interface.37 6.1.1 Overview.37 6.1.2 Bi-level discrete monitor interface .37 6.2 Bi-level switch monitor (BSM) interface.39 6.2.1 General principles.39 6.2.2 Bi-level switch monitor interface.40 7 Pulsed command interfaces.42 7.1 High power command (HPC) interfaces.42 7.1.1 General principles.42 7.1.2 High power command interface.42 7.1.3 Low voltage high power command (LV-HPC) electrical characteristics .43 7.1.4 High voltage high power command (HV-HPC) electrical characteristics.45 7.1.5 High current high power command (HC-HPC) electrical characteristics.46 7.1.6 Wiring type.47 7.1.7 High power command interface arrangement .47 7.2 Low power command (LPC) interface.48 7.2.1 General.48 7.2.2 Low power command interface.48 7.2.3 LPC electrical characteristics .49 7.2.4 Wiring type.50 7.2.5 Interface arrangement.50 8 Serial digital interfaces .51 8.1 Foreword .51 8.2 General principles of serial digital interfaces.51 8.2.1 Overview.51 8.2.2 General requirements.52 8.3 16-bit input serial digital (ISD) interface .53 8.3.1 16-bit input serial digital interface description.53 8.3.2 Signals skew.53 8.3.3 ISD interface timing specification .53 ECSSEST5014C 31July2008 6 8.3.4 16-bit input serial digital interface: signal description.56 8.4 16-bit output serial digital (OSD) interface description.58 8.4.1 16-bit output serial digital interface description .58 8.4.2 Signals skew.58 8.4.3 OSD interface timing specification.59 8.4.4 16-bit output serial digital interface signal description.60 8.5 16-bit bi-directional serial digital (BSD) interface description.62 8.6 Serial digital interface electrical circuits description .63 8.7 Balanced differential serial digital interface signals.64 8.7.1 Balanced differential serial digital interface - GATE_WRITE circuits .64 8.7.2 Balanced differential serial digital interface - DATA_CLK_OUT circuits.64 8.7.3 Balanced differential serial digital interface - DATA_OUT circuits.64 8.7.4 Balanced differential serial digital interface - DATA_IN circuits.65 8.7.5 Balanced differential serial digital interface - GATE_READ circuits.65 8.8 Serial digital interface circuit electrical characteristics.65 8.8.1 Introduction.65 8.8.2 Provisions.65 Annex A (informative) Tailoring guidelines.69 Bibliography.70 Figures Figure 3-1: Bit numbering convention .12 Figure 3-2: Timing diagram conventions.13 Figure 3-3: Signal timing and measurement references .14 Figure 4-1: Architectural context of interfaces defined in this standard.16 Figure 4-2: General scheme of redundant units cross-strapping .18 Figure 4-3: Example scheme for Single source Dual receiver cross-strapping.20 Figure 4-4: Example scheme for Dual source Single receiver cross-strapping.21 Figure 4-5: Cable capacitance definitions.22 Figure 5-1: Analogue signal monitor (single ended source) interface arrangement.27 Figure 5-2: Analogue signal monitor (differential source) interface arrangement .27 Figure 5-3: TSM1 reference model .30 Figure 5-4: Requirement for Rth/Rth as a function of RNORM and Rth. x = 0,01 .30 Figure 5-5: TSM1 interface arrangement .32 Figure 5-6: TSM2 interface arrangement .34 Figure 5-7: Example TSM1 and 4K3A354 thermistor.35 Figure 5-8: Example TSM1 and YSI44907 thermistor.35 ECSS